8-bit indirect accessing for SSD1928
Hardware = PIC24 Eval BrdC2

File:
zlgLogic_Trace1: PMPWaitBusy() enable under SetRegB(index, value). Time interval during CS is low as long as 1.07us!

zlgLogic_Trace2: PMPWaitBusy() disabled under SetRegB(index, value). This method didn't work simply because PMP failed to
setup properly for each WRITE action. Therefore no data has been written at all.

zlgLogic_Trace3: PMPWaitBusy() enabled but it has been modified to use nop instead of while(PMMODEbits.BUSY);
The efficiency should be boosting a lot because the time interval during CS is low was around 610ns. 

