* The HYNIX HY27(U/S)S(08/16)561A series is a 32Mx8bit NAND Flash with spare 8Mx16 bit capacity.
* Device contains 2048 blocks, composed by 32 pages consisting in two NAND structures of 16 series
* connected Flash cells. Thus, for our HY27US08561A NAND Flash, the memory cell array is arranged
* in a structure as (512+16) Bytes x 32 Pages x 2,048 Blocks. A Page size for x8 device is exactly
* (512+16 spare)Bytes, a block size is eq. Page*32, i.e. it is of (16K + 512 spare)Bytes.
* A picture is worth a thousand words. One may refer to a diagram accompanied this source code for 
* better details on this.
* 
* In contrast to NOR Flash, program and read operations are executed on a page basis 512bytes
* and the erase operation is executed on a block basis 16kBytes for NAND Flash. Bit-by-bit
* erase and program operations are prohibited.
*
* The 32M-byte physical space requires 24 address A0:A7, A9:A16, & A17:A24 thereby requiring
* 3 cycles for word-level addressing. They represent column address, low row address, 
* and high row address. 
*
* Address line A8 is missing because it is set to "LOW" or "HIGH" by the 0x00 or 0x01 command in
* the first cycle. One may refer to Page Read (nandRdPage()) and Page Write (nandWrPage()) functions 
* for details.