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Release Notes for STM32F4xx CMSIS

Copyright 2013 STMicroelectronics

 

Contents

  1. STM32F4xx CMSIS update History
  2. License

STM32F4xx CMSIS update History

V1.2.0RC3 / 21-June-2013

Main Changes

  • Add the support of STM32F401x devices.
  • stm32f4xx.h

    • Update  aspecific define for STM32F401xx devices "#define STM32F401X"

  • Add Startup file for STM32F401x Devices "startup_stm32f401x.s" for IAR and MD-ARM Toolchains

V1.2.0RC2 / 20-February-2013

Main Changes

  • Alpha 2 version for STM32F429x/439x devices.
  • stm32f4xx.h

    • Update bit definition for RCC and SAI registers.

    • Add the following bit definitions to enable ADC higher accuracy workaround (for more details please refer to AN4073):
      • PWR_CR_ADCDC1 in PWR_CR register.
      • SYSCFG_PMC_ADCxDC2 in SYSCFG_PMC register.
  • system_stm32f4xx.c

    • SystemInit_ExtMemCtl(): update FMC timing values and configuration for SDRAM and SRAM memories access

V1.2.0RC1 / 07-December-2012

Main Changes

  • Alpha 1 version for STM32F429x/439x devices.
  • stm32f4xx.h
    • Update  HSE_VALUE define value according to oscillator value integrated with Eval Board
    •  Update  devices name : #define STM32F40XX    /*!< STM32F40xx/41xx Devices */#define STM32F427X    /*!< STM32F427x/437x Devices */#define STM32F429X    /*!< STM32F429x/439x Devices */
  • system_stm32f4xx.c
    • Update system clock source to PLL/HSE clock (Update PLL Prescalers PLL_M value).

V1.1.0RC2 / 30-November-2012

Main Changes

  • stm32f4xx.h
    • Update  HSE_VALUE define value according to oscillator value integrated with Eval Board
    •  Replace all reference to "LCD" by "LTDC".
    • Update CRYP registers to be in line with  Reference Manual.
    • Update PWR registers bits definition to in line with Reference Manual
    • Update bits definition for RCC registers.
    • Add a the following legacy : #define STM32F4XX    STM32F40XX
  • system_stm32f4xx.c
    • Update system clock source to PLL/HSE clock (PLL/HSE = 168 Mhz).
    • Update the number of Wait state (5 wait state for SystemClock = 168 Mhz).
    • Add voltage scaling configuration according to system frequency and voltage used on VDD.

V1.1.0RC1 / 22-June-2012

Main Changes

  • Alpha 1 version for STM32F427x/437x devices.
  • stm32f4xx.h
    • Add support for STM32F427x/437x  devices:
      • Update product define: replace "#define STM32F4XX" by "#define STM32F40XX" for STM32F40x/41x devices
      •  Add new product define: "#define STM32F427X" for STM32F427x/437x devices.
      • Add new product define: "#define STM32F429X" for Big STM32F429x/439x devices.
      • Change the "#define HSE_VALUE" to 60 MHz to support FPGA platform.
      • Change the library version to V1.1.0RC1.
      • Add new IRQ to support Big Manta vector table.
      • Add new and update someTypedef to support new peripherals (DMA2D, FMC, LTDC, SAI)
      • Add new peripherals address mapping
      • Update bits definition
  • Add new startup files "startup_stm32f427x.s" and "startup_stm32f429x.s" for all toolchains
  • system_stm32f4xx.c
    • Update the system clock source to HSE and Update the SystemCoreClock variable to 60MHz.

V1.0.2 / 05-March-2012

Main Changes

  • All source files: license disclaimer text update and add link to the License file on ST Internet.

V1.0.1 / 28-December-2011

Main Changes

  • All source files: update disclaimer to add reference to the new license agreement
  • stm32f4xx.h
    • Correct bit definition: RCC_AHB2RSTR_HSAHRST changed to RCC_AHB2RSTR_HASHRST

V1.0.0 / 30-September-2011

Main Changes

  • First official release for STM32F40x/41x devices
  • Add startup file for TASKING toolchain
  • system_stm32f4xx.c: driver's comments update

V1.0.0RC2 / 26-September-2011

Main Changes

  • Official version (V1.0.0) Release Candidate2 for STM32F40x/41x devices
  • stm32f4xx.h
    • Add define for Cortex-M4 revision __CM4_REV
    • Correct RCC_CFGR_PPRE2_DIV16 bit (in RCC_CFGR register) value to 0x0000E000
    • Correct some bits definition to be in line with naming used in the Reference Manual (RM0090)
      • GPIO_OTYPER_IDR_x changed to GPIO_IDR_IDR_x
      • GPIO_OTYPER_ODR_x changed to GPIO_ODR_ODR_x
      • SYSCFG_PMC_MII_RMII changed to SYSCFG_PMC_MII_RMII_SEL
      • RCC_APB2RSTR_SPI1 changed to RCC_APB2RSTR_SPI1RST
      • DBGMCU_APB1_FZ_DBG_IWDEG_STOP changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
      • PWR_CR_PMODE changed to PWR_CR_VOS
      • PWR_CSR_REGRDY changed to PWR_CSR_VOSRDY
      • Add new define RCC_AHB1ENR_CCMDATARAMEN
      • Add new defines SRAM2_BASE, CCMDATARAM_BASE and BKPSRAM_BASE
    • GPIO_TypeDef structure: in the comment change AFR[2] address mapping to 0x20-0x24 instead of 0x24-0x28
  • system_stm32f4xx.c
    • SystemInit(): add code to enable the FPU
    • SetSysClock(): change PWR_CR_PMODE by PWR_CR_VOS
    • SystemInit_ExtMemCtl(): remove commented values
  • startup (for all compilers)
    • Delete code used to enable the FPU (moved to system_stm32f4xx.c file)
    • File’s header updated

V1.0.0RC1 / 25-August-2011

Main Changes

  • Official version (V1.0.0) Release Candidate1 for STM32F4xx devices

License

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

For complete documentation on STM32 Microcontrollers visit www.st.com/STM32