/*
**************************************************************************
* Date: 15th Oct 2007
* Target processor LPC210x (LPC2101/2/3)
**************************************************************************
*/

/*
**************************************************************************
* Date: 20th Oct 2007
* Add  Interrupt vector table &  VIC Interrupt channels constants
**************************************************************************
*/


/*
**************************************************************************
* Date: 24th Oct 2007
* Add  System Control/Status Flags Register 
* Change   FGPIO bit name
**************************************************************************
 */

#ifndef __IOCONFIG_H
#define __IOCONFIG_H

/* External interrupt register */
typedef struct {
  unsigned long EINT0           :1;
  unsigned long EINT1           :1;
  unsigned long EINT2           :1;
  unsigned long                 :29;
} __extint_bits;

/* External interrupt wakeup register */
typedef struct {
  unsigned long EXTWAKE0        :1;
  unsigned long EXTWAKE1        :1;
  unsigned long EXTWAKE2        :1;
  unsigned long                 :12;
  unsigned long RTCWAKE			:1;
  unsigned long					:16;
} __extwake_bits;

/* External interrupt mode register */
typedef struct {
  unsigned long EXTMODE0        :1;
  unsigned long EXTMODE1        :1;
  unsigned long EXTMODE2        :1;
  unsigned long                 :29;
} __extmode_bits;

/* External interrupt polarity register */
typedef struct {
  unsigned long EXTPOLAR0        :1;
  unsigned long EXTPOLAR1        :1;
  unsigned long EXTPOLAR2        :1;
  unsigned long                  :29;
} __extpol_bits;

/* System Control/Status Flags Register */
typedef struct{
  unsigned long GPIO0M  : 1;
  unsigned long         :31;
} __scs_bits;

/* Memory mapping control register */
typedef struct {
  unsigned long MAP             :2;
  unsigned long                 :30;
} __memmap_bits;

/* PLL control register */
typedef struct {
  unsigned long PLLE            :1;
  unsigned long PLLC            :1;
  unsigned long                 :30;
} __pllcon_bits;

/* PLL config register */
typedef struct {
  unsigned long MSEL            :5;
  unsigned long PSEL            :2;
  unsigned long                 :25;
} __pllcfg_bits;

/* PLL status register */
typedef struct {
  unsigned long MSEL            :5;
  unsigned long PSEL            :2;
  unsigned long                 :1;
  unsigned long PLLE            :1;
  unsigned long PLLC            :1;
  unsigned long PLOCK           :1;
  unsigned long                 :21;
} __pllstat_bits;

/* PLL feed register */
typedef struct {
  unsigned long FEED            :8;
  unsigned long                 :24;
} __pllfeed_bits;

/* Power control register */
typedef struct {
  unsigned long IDL             :1;
  unsigned long PD              :1;
  unsigned long                 :30;
} __pcon_bits;

/* Power Control For Peripherals Register */
typedef struct{
	unsigned long          : 1;
	unsigned long PCTIM0   : 1;
	unsigned long PCTIM1   : 1;
	unsigned long PCUART0  : 1;
	unsigned long PCUART1  : 1;
	unsigned long          : 2;
	unsigned long PCI2C0   : 1;
	unsigned long PCSPI    : 1;
	unsigned long PCRTC    : 1;
	unsigned long PCSSP    : 1;
	unsigned long          : 1;
	unsigned long PCAD     : 1;
	unsigned long          : 6;
	unsigned long PCI2C1   : 1;
	unsigned long          : 8;
	unsigned long PCTIM2   : 1;
	unsigned long PCTIM3   : 1;
	unsigned long          : 2;
} __pconp_bits;


/* Reset Source Identification Register */
typedef struct{
 unsigned long POR   : 1;
 unsigned long EXTR  : 1;
 unsigned long WDTR  : 1;
 unsigned long       :29;
} __rsir_bits;


/* APB Divider Register */
typedef struct{
 unsigned long APBDIV_ : 2;
 unsigned long         :30;
} __apbdiv_bits;


/* Memory accelerator module control register */
typedef struct {
  unsigned long MODECTRL        :2;
  unsigned long                 :30;
} __mamcr_bits;

/* Memory accelerator module timing register */
typedef struct {
  unsigned long CYCLES          :3;
  unsigned long                 :29;
} __mamtim_bits;


/* VIC Interrupt registers for LPC2101/2/3*/
typedef struct{
	unsigned long WDT   	: 1;
	unsigned long 		   	: 1;
	unsigned long ARMCORE0  : 1;
	unsigned long ARMCORE1  : 1;
	unsigned long TMR0   	: 1;
	unsigned long TMR1   	: 1;
	unsigned long UART0   	: 1;
	unsigned long UART1   	: 1;
	unsigned long 		   	: 1;
	unsigned long I2C0   	: 1;
	unsigned long SPI0  	: 1;
	unsigned long SSP	  	: 1;
	unsigned long PLL  		: 1;
	unsigned long RTC		: 1;
	unsigned long EINT0  	: 1;
	unsigned long EINT1  	: 1;
	unsigned long EINT2  	: 1;
	unsigned long 		  	: 1;
	unsigned long AD0  		: 1;
	unsigned long I2C1		: 1;
	unsigned long   		: 6;
	unsigned long TMR2		: 1;
	unsigned long TMR3		: 1;
	unsigned long 			: 4;
} __vicint_bits;


/* VIC Vector control registers */
typedef struct{
	unsigned long NUMBER   : 5;
	unsigned long ENABLED  : 1;
	unsigned long          : 26;
} __vicvectcntl_bits;


/* VIC protection enable register */
typedef struct{
	unsigned long VIC_ACCESS: 1;
	unsigned long    		: 31;
} __vicprotection_bits;


/* Pin function select register 0 */
typedef struct {
  unsigned long P0_0            :2;
  unsigned long P0_1            :2;
  unsigned long P0_2            :2;
  unsigned long P0_3            :2;
  unsigned long P0_4            :2;
  unsigned long P0_5            :2;
  unsigned long P0_6            :2;
  unsigned long P0_7            :2;
  unsigned long P0_8            :2;
  unsigned long P0_9            :2;
  unsigned long P0_10           :2;
  unsigned long P0_11           :2;
  unsigned long P0_12           :2;
  unsigned long P0_13           :2;
  unsigned long P0_14           :2;
  unsigned long P0_15           :2;
} __pinsel0_bits;

/* Pin function select register 1 */
typedef struct {
  unsigned long P0_16           :2;
  unsigned long P0_17           :2;
  unsigned long P0_18           :2;
  unsigned long P0_19           :2;
  unsigned long P0_20           :2;
  unsigned long P0_21           :2;
  unsigned long P0_22           :2;
  unsigned long P0_23           :2;
  unsigned long P0_24           :2;
  unsigned long P0_25           :2;
  unsigned long P0_26           :2;
  unsigned long P0_27           :2;
  unsigned long P0_28           :2;
  unsigned long P0_29           :2;
  unsigned long P0_30           :2;
  unsigned long P0_31           :2;
} __pinsel1_bits;


/* GPIO registers */
typedef struct{ 
  unsigned long P0_0            :1;
  unsigned long P0_1            :1;
  unsigned long P0_2            :1;
  unsigned long P0_3            :1;
  unsigned long P0_4            :1;
  unsigned long P0_5            :1;
  unsigned long P0_6            :1;
  unsigned long P0_7            :1;
  unsigned long P0_8            :1;
  unsigned long P0_9            :1;
  unsigned long P0_10           :1;
  unsigned long P0_11           :1;
  unsigned long P0_12           :1;
  unsigned long P0_13           :1;
  unsigned long P0_14           :1;
  unsigned long P0_15           :1;
  unsigned long P0_16           :1;
  unsigned long P0_17           :1;
  unsigned long P0_18           :1;
  unsigned long P0_19           :1;
  unsigned long P0_20           :1;
  unsigned long P0_21           :1;
  unsigned long P0_22           :1;
  unsigned long P0_23           :1;
  unsigned long P0_24           :1;
  unsigned long P0_25           :1;
  unsigned long P0_26           :1;
  unsigned long P0_27           :1;
  unsigned long P0_28           :1;
  unsigned long P0_29           :1;
  unsigned long P0_30           :1;
  unsigned long P0_31           :1;
} __gpio_bits;


/* FGPIO Registers */
typedef union{
 struct {
 	unsigned long P0_0   : 1;
 	unsigned long P0_1   : 1;
 	unsigned long P0_2   : 1;
 	unsigned long P0_3   : 1;
 	unsigned long P0_4   : 1;
 	unsigned long P0_5   : 1;
 	unsigned long P0_6   : 1;
 	unsigned long P0_7   : 1;
 	unsigned long P0_8   : 1;
 	unsigned long P0_9   : 1;
 	unsigned long P0_10  : 1;
 	unsigned long P0_11  : 1;
 	unsigned long P0_12  : 1;
 	unsigned long P0_13  : 1;
 	unsigned long P0_14  : 1;
 	unsigned long P0_15  : 1;
 	unsigned long P0_16  : 1;
 	unsigned long P0_17  : 1;
 	unsigned long P0_18  : 1;
 	unsigned long P0_19  : 1;
 	unsigned long P0_20  : 1;
 	unsigned long P0_21  : 1;
 	unsigned long P0_22  : 1;
 	unsigned long P0_23  : 1;
 	unsigned long P0_24  : 1;
 	unsigned long P0_25  : 1;
 	unsigned long P0_26  : 1;
 	unsigned long P0_27  : 1;
 	unsigned long P0_28  : 1;
 	unsigned long P0_29  : 1;
 	unsigned long P0_30  : 1;
 	unsigned long P0_31  : 1;
  } __gpio_bits;

 struct
  {
    union
    {
      struct{
         unsigned char  P0_0   : 1;
         unsigned char  P0_1   : 1;
         unsigned char  P0_2   : 1;
         unsigned char  P0_3   : 1;
         unsigned char  P0_4   : 1;
         unsigned char  P0_5   : 1;
         unsigned char  P0_6   : 1;
         unsigned char  P0_7   : 1;
      } __byte0_bit;
       unsigned char __byte0;
    } __BYTE0;
    union
    {
      struct{
         unsigned char  P0_8   : 1;
         unsigned char  P0_9   : 1;
         unsigned char  P0_10  : 1;
         unsigned char  P0_11  : 1;
         unsigned char  P0_12  : 1;
         unsigned char  P0_13  : 1;
         unsigned char  P0_14  : 1;
         unsigned char  P0_15  : 1;
      } __byte1_bit;

       unsigned char __byte1;
    } __BYTE1;
    union
    {
      struct{
         unsigned char  P0_16  : 1;
         unsigned char  P0_17  : 1;
         unsigned char  P0_18  : 1;
         unsigned char  P0_19  : 1;
         unsigned char  P0_20  : 1;
         unsigned char  P0_21  : 1;
         unsigned char  P0_22  : 1;
         unsigned char  P0_23  : 1;
      } __byte2_bit;
       unsigned char __byte2;
    } __BYTE2;
    union
    {
      struct{
         unsigned char  P0_24  : 1;
         unsigned char  P0_25  : 1;
         unsigned char  P0_26  : 1;
         unsigned char  P0_27  : 1;
         unsigned char  P0_28  : 1;
         unsigned char  P0_29  : 1;
         unsigned char  P0_30  : 1;
         unsigned char  P0_31  : 1;
      } __byte3_bit;
       unsigned char __byte3;
    } __BYTE3;
  } __fgpio_bytes;

  struct
  {
    union
    {
      struct{
         unsigned short P0_0   : 1;
         unsigned short P0_1   : 1;
         unsigned short P0_2   : 1;
         unsigned short P0_3   : 1;
         unsigned short P0_4   : 1;
         unsigned short P0_5   : 1;
         unsigned short P0_6   : 1;
         unsigned short P0_7   : 1;
         unsigned short P0_8   : 1;
         unsigned short P0_9   : 1;
         unsigned short P0_10  : 1;
         unsigned short P0_11  : 1;
         unsigned short P0_12  : 1;
         unsigned short P0_13  : 1;
         unsigned short P0_14  : 1;
         unsigned short P0_15  : 1;
      } __shortl_bit;
       unsigned short __shortl;
    } __SHORTL;
    union
    {
      struct{
         unsigned short P0_16   : 1;
         unsigned short P0_17  : 1;
         unsigned short P0_18  : 1;
         unsigned short P0_19  : 1;
         unsigned short P0_20  : 1;
         unsigned short P0_21  : 1;
         unsigned short P0_22  : 1;
         unsigned short P0_23  : 1;
         unsigned short P0_24  : 1;
         unsigned short P0_25  : 1;
         unsigned short P0_26  : 1;
         unsigned short P0_27  : 1;
         unsigned short P0_28  : 1;
         unsigned short P0_29  : 1;
         unsigned short P0_30  : 1;
         unsigned short P0_31  : 1;
      } __shortu_bit;
       unsigned short __shortu;
    } __SHORTU;
  } __fgpio_shorts;
} __fgpio_bits;

/* UART Fractional Divider Register */
typedef struct{
 unsigned long DIVADDVAL  : 4;
 unsigned long MULVAL     : 4;
 unsigned long            :24;
} __uartfdr_bits;

/* UART Interrupt Enable Register */
typedef struct{
 unsigned long RDAIE      : 1;
 unsigned long THREIE     : 1;
 unsigned long RXLSIE     : 1;
 unsigned long            : 5;
 unsigned long ABTOIntEn  : 1;
 unsigned long ABEOIntEn  : 1;
 unsigned long            :22;
} __uartier0_bits;

/* UART Interrupt Enable Register */
typedef struct{
 unsigned long RDAIE      : 1;
 unsigned long THREIE     : 1;
 unsigned long RXLSIE     : 1;
 unsigned long MSIE       : 1;
 unsigned long            : 3;
 unsigned long CTSIE      : 1;
 unsigned long ABTOIntEn  : 1;
 unsigned long ABEOIntEn  : 1;
 unsigned long            :22;
} __uartier1_bits;

/* UART Interrupt Identification Register and Fifo Control Register */
typedef union{
  /* UxIIR */
  struct {
 unsigned long IP       : 1;
 unsigned long IID      : 3;
 unsigned long          : 2;
 unsigned long IIRFE    : 2;
 unsigned long ABEOInt  : 1;
 unsigned long ABTOInt  : 1;
 unsigned long          :22;
  } __uxiir_bits;
  /* UxFCR */
  struct {
 unsigned long FCRFE    : 1;
 unsigned long RFR      : 1;
 unsigned long TFR      : 1;
 unsigned long          : 3;
 unsigned long RTLS     : 2;
 unsigned long          :24;
  } __uxfcr_bits;
} __uartfcriir_bits;

/* UART Line Control Register */
typedef struct{
 unsigned  char  WLS   : 2;
 unsigned  char  SBS   : 1;
 unsigned  char  PE    : 1;
 unsigned  char  PS    : 2;
 unsigned  char  BC    : 1;
 unsigned  char  DLAB  : 1;
} __uartlcr_bits;

/* UART Line Status Register */
typedef struct{
 unsigned  char  DR    : 1;
 unsigned  char  OE    : 1;
 unsigned  char  PE    : 1;
 unsigned  char  FE    : 1;
 unsigned  char  BI    : 1;
 unsigned  char  THRE  : 1;
 unsigned  char  TEMT  : 1;
 unsigned  char  RXFE  : 1;
} __uartlsr_bits;

/* UART Auto-baud Control Register */
typedef struct{
 unsigned long Start        : 1;
 unsigned long Mode         : 1;
 unsigned long AutoRestart  : 1;
 unsigned long              : 5;
 unsigned long ABEOIntClr   : 1;
 unsigned long ABTOIntClr   : 1;
 unsigned long              :22;
} __uartacr_bits;

/* UART Transmit Enable Register */
typedef struct{
 unsigned  char        : 7;
 unsigned  char  TXEN  : 1;
} __uartter_bits;

/* UART Modem Control Register */
typedef struct{
 unsigned  char  DTR    : 1;
 unsigned  char  RTS    : 1;
 unsigned  char         : 2;
 unsigned  char  LMS    : 1;
 unsigned  char         : 1;
 unsigned  char  RTSen  : 1;
 unsigned  char  CTSen  : 1;
} __uartmcr_bits;

/* UART Modem Status Register */
typedef union{
  //U1MSR
  struct {
 unsigned  char  DCTS  : 1;
 unsigned  char  DDSR  : 1;
 unsigned  char  TERI  : 1;
 unsigned  char  DDCD  : 1;
 unsigned  char  CTS   : 1;
 unsigned  char  DSR   : 1;
 unsigned  char  RI    : 1;
 unsigned  char  DCD   : 1;
  } __modemctrl_bits;
  //U1MSR
  struct {
 unsigned  char  MSR0  : 1;
 unsigned  char  MSR1  : 1;
 unsigned  char  MSR2  : 1;
 unsigned  char  MSR3  : 1;
 unsigned  char  MSR4  : 1;
 unsigned  char  MSR5  : 1;
 unsigned  char  MSR6  : 1;
 unsigned  char  MSR7  : 1;
  } __u1msr_bits;
} __uartmsr_bits;

/* I2C Control Set Register */
typedef struct{
 unsigned long       : 2;
 unsigned long AA    : 1;
 unsigned long SI    : 1;
 unsigned long STO   : 1;
 unsigned long STA   : 1;
 unsigned long I2EN  : 1;
 unsigned long       :25;
} __i2conset_bits;

/* I2C Control Clear Register */
typedef struct{
 unsigned long        : 2;
 unsigned long AAC    : 1;
 unsigned long SIC    : 1;
 unsigned long        : 1;
 unsigned long STAC   : 1;
 unsigned long I2ENC  : 1;
 unsigned long        :25;
} __i2conclr_bits;

/* I2C Status Register */
typedef struct{
 unsigned long STATUS  : 8;
 unsigned long         :24;
} __i2stat_bits;

/* I2C Data Register */
typedef struct{
 unsigned long DATA  : 8;
 unsigned long       :24;
} __i2dat_bits;

/* I2C Slave Address Register */
typedef struct{
 unsigned long GC    : 1;
 unsigned long ADDR  : 7;
 unsigned long       :24;
} __i2adr_bits;

/* I2C SCL Duty Cycle Register */
typedef struct{
 unsigned long COUNT  :16;
 unsigned long        :16;
} __i2scl_bits;

/* SPI Control Register */
typedef struct{
 unsigned long         : 2;
 unsigned long BitEna  : 1;
 unsigned long CPHA    : 1;
 unsigned long CPOL    : 1;
 unsigned long MSTR    : 1;
 unsigned long LSBF    : 1;
 unsigned long SPIE    : 1;
 unsigned long BITS    : 4;
 unsigned long         :20;
} __spcr_bits;

/* SPI Status Register */
typedef struct{
 unsigned long       : 3;
 unsigned long ABRT  : 1;
 unsigned long MODF  : 1;
 unsigned long ROVR  : 1;
 unsigned long WCOL  : 1;
 unsigned long SPIF  : 1;
 unsigned long       :24;
} __spsr_bits;

/* SPI Data Register */
typedef struct{
 unsigned long DATA  :16;
 unsigned long       :16;
} __spdr_bits;

/* SPI Clock Counter Register */
typedef struct{
 unsigned long COUNTER  : 8;
 unsigned long          :24;
} __spccr_bits;

/* SPI Interrupt Register */
typedef struct{
 unsigned long SPIINT  : 1;
 unsigned long         :31;
} __spint_bits;

/* SSP Control Register 0 */
typedef struct{
 unsigned long DSS   : 4;
 unsigned long FRF   : 2;
 unsigned long CPOL  : 1;
 unsigned long CPHA  : 1;
 unsigned long SCR   : 8;
 unsigned long       :16;
} __sspcr0_bits;

/* SSP Control Register 1 */
typedef struct{
 unsigned long LBM  : 1;
 unsigned long SSE  : 1;
 unsigned long MS   : 1;
 unsigned long SOD  : 1;
 unsigned long      :28;
} __sspcr1_bits;

/* SSP Data Register */
typedef struct{
 unsigned long DATA  :16;
 unsigned long       :16;
} __sspdr_bits;

/* SSP Status Register */
typedef struct{
 unsigned long TFE  : 1;
 unsigned long TNF  : 1;
 unsigned long RNE  : 1;
 unsigned long RNF  : 1;
 unsigned long BSY  : 1;
 unsigned long      :27;
} __sspsr_bits;

/* SSP Clock Prescale Register */
typedef struct{
 unsigned long CPSDVSR  : 8;
 unsigned long          :24;
} __sspcpsr_bits;

/* SSP Interrupt Mask Set/Clear Register */
typedef struct{
 unsigned long RORIM  : 1;
 unsigned long RTIM   : 1;
 unsigned long RXIM   : 1;
 unsigned long TXIM   : 1;
 unsigned long        :28;
} __sspimsc_bits;

/* SSP Raw Interrupt Status Register */
typedef struct{
 unsigned long RORRIS  : 1;
 unsigned long RTRIS   : 1;
 unsigned long RXRIS   : 1;
 unsigned long TXRIS   : 1;
 unsigned long         :28;
} __sspris_bits;

/* SSP Masked Interrupt Register */
typedef struct{
 unsigned long RORMIS  : 1;
 unsigned long RTMIS   : 1;
 unsigned long RXMIS   : 1;
 unsigned long TXMIS   : 1;
 unsigned long         :28;
} __sspmis_bits;

/* SSP Interrupt Clear Registerr */
typedef struct{
 unsigned long RORIC  : 1;
 unsigned long RTIC   : 1;
 unsigned long        :30;
} __sspicr_bits;

/* A/D Control Register */
typedef struct{
 unsigned long SEL     : 8;
 unsigned long CLKDIV  : 8;
 unsigned long BURST   : 1;
 unsigned long CLKS    : 3;
 unsigned long         : 1;
 unsigned long PDN     : 1;
 unsigned long         : 2;
 unsigned long START   : 3;
 unsigned long EDGE    : 1;
 unsigned long         : 4;
} __adcr_bits;

/* A/D Global Data Register */
typedef struct{
 unsigned long         : 6;
 unsigned long RESULT  :10;
 unsigned long         : 8;
 unsigned long CHN     : 3;
 unsigned long         : 3;
 unsigned long OVERUN  : 1;
 unsigned long DONE    : 1;
} __adgdr_bits;

/* A/D Status Register */
typedef struct{
 unsigned long DONE0     : 1;
 unsigned long DONE1     : 1;
 unsigned long DONE2     : 1;
 unsigned long DONE3     : 1;
 unsigned long DONE4     : 1;
 unsigned long DONE5     : 1;
 unsigned long DONE6     : 1;
 unsigned long DONE7     : 1;
 unsigned long OVERRUN0  : 1;
 unsigned long OVERRUN1  : 1;
 unsigned long OVERRUN2  : 1;
 unsigned long OVERRUN3  : 1;
 unsigned long OVERRUN4  : 1;
 unsigned long OVERRUN5  : 1;
 unsigned long OVERRUN6  : 1;
 unsigned long OVERRUN7  : 1;
 unsigned long ADINT     : 1;
 unsigned long           :15;
} __adstat_bits;

/* A/D Intrrupt Enable Register */
typedef struct{
 unsigned long ADINTEN0  : 1;
 unsigned long ADINTEN1  : 1;
 unsigned long ADINTEN2  : 1;
 unsigned long ADINTEN3  : 1;
 unsigned long ADINTEN4  : 1;
 unsigned long ADINTEN5  : 1;
 unsigned long ADINTEN6  : 1;
 unsigned long ADINTEN7  : 1;
 unsigned long ADGINTEN  : 1;
 unsigned long           :23;
} __adinten_bits;

/* A/D Data Register */
typedef struct{
 unsigned long         : 6;
 unsigned long RESULT  :10;
 unsigned long         :14;
 unsigned long OVERUN  : 1;
 unsigned long DONE    : 1;
} __addr_bits;

/* TIMER0 Interrupt Register */
typedef struct{
 unsigned long MR0INT  : 1;
 unsigned long MR1INT  : 1;
 unsigned long MR2INT  : 1;
 unsigned long MR3INT  : 1;
 unsigned long CR0INT  : 1;
 unsigned long CR1INT  : 1;
 unsigned long CR2INT  : 1;
 unsigned long         :25;
} __ir0_bits;

/* TIMER1 Interrupt Register */
typedef struct{
 unsigned long MR0INT  : 1;
 unsigned long MR1INT  : 1;
 unsigned long MR2INT  : 1;
 unsigned long MR3INT  : 1;
 unsigned long CR0INT  : 1;
 unsigned long CR1INT  : 1;
 unsigned long CR2INT  : 1;
 unsigned long CR3INT  : 1;
 unsigned long         :24;
} __ir1_bits;

/* TIMER3 Interrupt Register */
typedef struct{
 unsigned long MR0INT  : 1;
 unsigned long MR1INT  : 1;
 unsigned long MR2INT  : 1;
 unsigned long MR3INT  : 1;
 unsigned long         :28;
} __ir3_bits;

/* TIMER Control Register */
typedef struct{
 unsigned long CE  : 1;
 unsigned long CR  : 1;
 unsigned long     :30;
} __tcr_bits;

/* TIMER Count Control Register */
typedef struct{
 unsigned long TM   : 2;
 unsigned long CIS  : 2;
 unsigned long      :28;
} __tctcr_bits;

/* TIMER Match Control Register */
typedef struct{
 unsigned long MR0INT   : 1;
 unsigned long MR0RES   : 1;
 unsigned long MR0STOP  : 1;
 unsigned long MR1INT   : 1;
 unsigned long MR1RES   : 1;
 unsigned long MR1STOP  : 1;
 unsigned long MR2INT   : 1;
 unsigned long MR2RES   : 1;
 unsigned long MR2STOP  : 1;
 unsigned long MR3INT   : 1;
 unsigned long MR3RES   : 1;
 unsigned long MR3STOP  : 1;
 unsigned long          :20;
} __mcr_bits;

/* TIMER0 Capture Control Register */
typedef struct{
 unsigned long CAP0RE   : 1;
 unsigned long CAP0FE   : 1;
 unsigned long CAP0INT  : 1;
 unsigned long CAP1RE   : 1;
 unsigned long CAP1FE   : 1;
 unsigned long CAP1INT  : 1;
 unsigned long CAP2RE   : 1;
 unsigned long CAP2FE   : 1;
 unsigned long CAP2INT  : 1;
 unsigned long          :23;
} __ccr0_bits;

/* TIMER1 Capture Control Register */
typedef struct{
 unsigned long CAP0RE   : 1;
 unsigned long CAP0FE   : 1;
 unsigned long CAP0INT  : 1;
 unsigned long CAP1RE   : 1;
 unsigned long CAP1FE   : 1;
 unsigned long CAP1INT  : 1;
 unsigned long CAP2RE   : 1;
 unsigned long CAP2FE   : 1;
 unsigned long CAP2INT  : 1;
 unsigned long CAP3RE   : 1;
 unsigned long CAP3FE   : 1;
 unsigned long CAP3INT  : 1;
 unsigned long          :20;
} __ccr1_bits;

/* TIMER External Match Register */
typedef struct{
 unsigned long EM0   : 1;
 unsigned long EM1   : 1;
 unsigned long EM2   : 1;
 unsigned long EM3   : 1;
 unsigned long EMC0  : 2;
 unsigned long EMC1  : 2;
 unsigned long EMC2  : 2;
 unsigned long EMC3  : 2;
 unsigned long       :20;
} __emr_bits;

/* TIMER PWM Control Register */
typedef struct{
 unsigned long PWM0ENA  : 1;
 unsigned long PWM1ENA  : 1;
 unsigned long PWM2ENA  : 1;
 unsigned long PWM3ENA  : 1;
 unsigned long          :28;
} __tpwrcon_bits;

/* RTC Interrupt Location Register */
typedef struct{
 unsigned long RTCCIF  : 1;
 unsigned long RTCALF  : 1;
 unsigned long         :30;
} __ilr_bits;

/* RTC Clock Tick Counter Register */
typedef struct{
 unsigned long COUNTER  :16;
 unsigned long          :16;
} __ctc_bits;

/* RTC Clock Control Register */
typedef struct{
 unsigned long CLKEN   : 1;
 unsigned long CTCRST  : 1;
 unsigned long CTTEST  : 2;
 unsigned long CLKSRC  : 1;
 unsigned long         :27;
} __rtcccr_bits;

/* RTC Counter Increment Interrupt Register */
typedef struct{
 unsigned long IMSEC   : 1;
 unsigned long IMMIN   : 1;
 unsigned long IMHOUR  : 1;
 unsigned long IMDOM   : 1;
 unsigned long IMDOW   : 1;
 unsigned long IMDOY   : 1;
 unsigned long IMMON   : 1;
 unsigned long IMYEAR  : 1;
 unsigned long         :24;
} __ciir_bits;

/* RTC Alarm Mask Register */
typedef struct{
 unsigned long AMRSEC   : 1;
 unsigned long AMRMIN   : 1;
 unsigned long AMRHOUR  : 1;
 unsigned long AMRDOM   : 1;
 unsigned long AMRDOW   : 1;
 unsigned long AMRDOY   : 1;
 unsigned long AMRMON   : 1;
 unsigned long AMRYEAR  : 1;
 unsigned long          :24;
} __amr_bits;

/* RTC Consolidated Time Register 0 */
typedef struct{
 unsigned long SEC_   : 6;
 unsigned long       : 2;
 unsigned long MIN_   : 6;
 unsigned long       : 2;
 unsigned long HOUR_  : 5;
 unsigned long       : 3;
 unsigned long DOW_   : 3;
 unsigned long       : 5;
} __ctime0_bits;

/* RTC Consolidated Time Register 1 */
typedef struct{
 unsigned long DOM_   : 5;
 unsigned long       : 3;
 unsigned long MON_   : 4;
 unsigned long       : 4;
 unsigned long YEAR_  :12;
 unsigned long       : 4;
} __ctime1_bits;

/* RTC Consolidated Time Register 2 */
typedef struct{
 unsigned long DOY_  :12;
 unsigned long      :20;
} __ctime2_bits;

/* RTC Second Register */
typedef struct{
 unsigned long SEC_  : 6;
 unsigned long      :26;
} __sec_bits;

/* RTC Minute Register */
typedef struct{
 unsigned long MIN_  : 6;
 unsigned long      :26;
} __min_bits;

/* RTC Hour Register */
typedef struct{
 unsigned long HOUR_  : 5;
 unsigned long       :27;
} __hour_bits;

/* RTC Day Of Month Register */
typedef struct{
 unsigned long DOM_  : 5;
 unsigned long      :27;
} __dom_bits;

/* RTC Day Of Week Register */
typedef struct{
 unsigned long DOW_  : 3;
 unsigned long      :29;
} __dow_bits;

/* RTC Day Of Year Register */
typedef struct{
 unsigned long DOY_  : 9;
 unsigned long      :23;
} __doy_bits;

/* RTC Month Register */
typedef struct{
 unsigned long MON_  : 4;
 unsigned long      :28;
} __month_bits;

/* RTC Year Register */
typedef struct{
 unsigned long YEAR_  :12;
 unsigned long       :20;
} __year_bits;

/* RTC Prescaler Value, Integer Portion Register */
typedef struct{
 unsigned long VALUE  :13;
 unsigned long        :19;
} __preint_bits;

/* RTC Prescaler Value, Fractional Portion Register */
typedef struct{
 unsigned long VALUE  :15;
 unsigned long        :17;
} __prefrac_bits;

/* Watchdog Mode Register */
typedef struct{
 unsigned long WDEN     : 1;
 unsigned long WDRESET  : 1;
 unsigned long WDTOF    : 1;
 unsigned long WDINT    : 1;
 unsigned long          :28;
} __wdmod_bits;

/* Watchdog Feed Register */
typedef struct{
 unsigned long FEED  : 8;
 unsigned long       :24;
} __wdfeed_bits;



/* Common declarations  ****************************************************/


/***************************************************************************
 **
 ** VIC
 **
 ***************************************************************************/
#define VICIRQStatus_bit   (*((volatile __vicint_bits *) 0xFFFFF000))
#define VICFIQStatus_bit   (*((volatile __vicint_bits *) 0xFFFFF004))
#define VICRawIntr_bit     (*((volatile __vicint_bits *) 0xFFFFF008))
#define VICIntSelect_bit   (*((volatile __vicint_bits *) 0xFFFFF00C))
#define VICIntEnable_bit   (*((volatile __vicint_bits *) 0xFFFFF010))
#define VICIntEnClr_bit    (*((volatile __vicint_bits *) 0xFFFFF014))
#define VICSoftInt_bit     (*((volatile __vicint_bits *) 0xFFFFF018))
#define VICSoftIntClr_bit  (*((volatile __vicint_bits *) 0xFFFFF01C))
#define VICProtection_bit  (*((volatile __vicprotection_bits *) 0xFFFFF020))
#define VICVectCntl0_bit   (*((volatile __vicvectcntl_bits *) 0xFFFFF200))
#define VICVectCntl1_bit   (*((volatile __vicvectcntl_bits *) 0xFFFFF204))
#define VICVectCntl2_bit   (*((volatile __vicvectcntl_bits *) 0xFFFFF208))
#define VICVectCntl3_bit   (*((volatile __vicvectcntl_bits *) 0xFFFFF20C))
#define VICVectCntl4_bit   (*((volatile __vicvectcntl_bits *) 0xFFFFF210))
#define VICVectCntl5_bit   (*((volatile __vicvectcntl_bits *) 0xFFFFF214))
#define VICVectCntl6_bit   (*((volatile __vicvectcntl_bits *) 0xFFFFF218))
#define VICVectCntl7_bit   (*((volatile __vicvectcntl_bits *) 0xFFFFF21C))
#define VICVectCntl8_bit   (*((volatile __vicvectcntl_bits *) 0xFFFFF220))
#define VICVectCntl9_bit   (*((volatile __vicvectcntl_bits *) 0xFFFFF224))
#define VICVectCntl10_bit  (*((volatile __vicvectcntl_bits *) 0xFFFFF228))
#define VICVectCntl11_bit  (*((volatile __vicvectcntl_bits *) 0xFFFFF22C))
#define VICVectCntl12_bit  (*((volatile __vicvectcntl_bits *) 0xFFFFF230))
#define VICVectCntl13_bit  (*((volatile __vicvectcntl_bits *) 0xFFFFF234))
#define VICVectCntl14_bit  (*((volatile __vicvectcntl_bits *) 0xFFFFF238))
#define VICVectCntl15_bit  (*((volatile __vicvectcntl_bits *) 0xFFFFF23C))

/* Pin Connect Block */
#define PINSEL0_bit        (*((volatile __pinsel0_bits *) 0xE002C000))
#define PINSEL1_bit        (*((volatile __pinsel1_bits *) 0xE002C004))


/* General Purpose Input/Output (GPIO) */
#define IOPIN_bit          (*((volatile __gpio_bits *) 0xE0028000))
#define IOSET_bit          (*((volatile __gpio_bits *) 0xE0028004))
#define IODIR_bit          (*((volatile __gpio_bits *) 0xE0028008))
#define IOCLR_bit          (*((volatile __gpio_bits *) 0xE002800C))

/* Fast General Purpose Input/Output (GPIO) */
#define FIODIR_bit	       (*((volatile __fgpio_bits *) 0x3FFFC000))
#define FIODIR0           FIODIR_bit.__fgpio_bytes.__BYTE0.__byte0
#define FIODIR0_bit       FIODIR_bit.__fgpio_bytes.__BYTE0.__byte0_bit
#define FIODIR1           FIODIR_bit.__fgpio_bytes.__BYTE1.__byte1
#define FIODIR1_bit       FIODIR_bit.__fgpio_bytes.__BYTE1.__byte1_bit
#define FIODIR2           FIODIR_bit.__fgpio_bytes.__BYTE2.__byte2
#define FIODIR2_bit       FIODIR_bit.__fgpio_bytes.__BYTE2.__byte2_bit
#define FIODIR3           FIODIR_bit.__fgpio_bytes.__BYTE3.__byte3
#define FIODIR3_bit       FIODIR_bit.__fgpio_bytes.__BYTE3.__byte3_bit
#define FIODIRL           FIODIR_bit.__fgpio_shorts.__SHORTL.__shortl
#define FIODIRL_bit       FIODIR_bit.__fgpio_shorts.__SHORTL.__shortl_bit
#define FIODIRU           FIODIR_bit.__fgpio_shorts.__SHORTU.__shortu
#define FIODIRU_bit       FIODIR_bit.__fgpio_shorts.__SHORTU.__shortu_bit

#define FIOMASK_bit        (*((volatile __fgpio_bits *) 0x3FFFC010))
#define FIOMASK0           FIOMASK_bit.__fgpio_bytes.__BYTE0.__byte0
#define FIOMASK0_bit       FIOMASK_bit.__fgpio_bytes.__BYTE0.__byte0_bit
#define FIOMASK1           FIOMASK_bit.__fgpio_bytes.__BYTE1.__byte1
#define FIOMASK1_bit       FIOMASK_bit.__fgpio_bytes.__BYTE1.__byte1_bit
#define FIOMASK2           FIOMASK_bit.__fgpio_bytes.__BYTE2.__byte2
#define FIOMASK2_bit       FIOMASK_bit.__fgpio_bytes.__BYTE2.__byte2_bit
#define FIOMASK3           FIOMASK_bit.__fgpio_bytes.__BYTE3.__byte3
#define FIOMASK3_bit       FIOMASK_bit.__fgpio_bytes.__BYTE3.__byte3_bit
#define FIOMASKL           FIOMASK_bit.__fgpio_shorts.__SHORTL.__shortl
#define FIOMASKL_bit       FIOMASK_bit.__fgpio_shorts.__SHORTL.__shortl_bit
#define FIOMASKU           FIOMASK_bit.__fgpio_shorts.__SHORTU.__shortu
#define FIOMASKU_bit       FIOMASK_bit.__fgpio_shorts.__SHORTU.__shortu_bit

#define FIOPIN_bit         (*((volatile __fgpio_bits *) 0x3FFFC014))
#define FIOPIN0           FIOPIN_bit.__fgpio_bytes.__BYTE0.__byte0
#define FIOPIN0_bit       FIOPIN_bit.__fgpio_bytes.__BYTE0.__byte0_bit
#define FIOPIN1           FIOPIN_bit.__fgpio_bytes.__BYTE1.__byte1
#define FIOPIN1_bit       FIOPIN_bit.__fgpio_bytes.__BYTE1.__byte1_bit
#define FIOPIN2           FIOPIN_bit.__fgpio_bytes.__BYTE2.__byte2
#define FIOPIN2_bit       FIOPIN_bit.__fgpio_bytes.__BYTE2.__byte2_bit
#define FIOPIN3           FIOPIN_bit.__fgpio_bytes.__BYTE3.__byte3
#define FIOPIN3_bit       FIOPIN_bit.__fgpio_bytes.__BYTE3.__byte3_bit
#define FIOPINL           FIOPIN_bit.__fgpio_shorts.__SHORTL.__shortl
#define FIOPINL_bit       FIOPIN_bit.__fgpio_shorts.__SHORTL.__shortl_bit
#define FIOPINU           FIOPIN_bit.__fgpio_shorts.__SHORTU.__shortu
#define FIOPINU_bit       FIOPIN_bit.__fgpio_shorts.__SHORTU.__shortu_bit

#define FIOSET_bit         (*((volatile __fgpio_bits *) 0x3FFFC018))
#define FIOSET0           FIOSET_bit.__fgpio_bytes.__BYTE0.__byte0
#define FIOSET0_bit       FIOSET_bit.__fgpio_bytes.__BYTE0.__byte0_bit
#define FIOSET1           FIOSET_bit.__fgpio_bytes.__BYTE1.__byte1
#define FIOSET1_bit       FIOSET_bit.__fgpio_bytes.__BYTE1.__byte1_bit
#define FIOSET2           FIOSET_bit.__fgpio_bytes.__BYTE2.__byte2
#define FIOSET2_bit       FIOSET_bit.__fgpio_bytes.__BYTE2.__byte2_bit
#define FIOSET3           FIOSET_bit.__fgpio_bytes.__BYTE3.__byte3
#define FIOSET3_bit       FIOSET_bit.__fgpio_bytes.__BYTE3.__byte3_bit
#define FIOSETL           FIOSET_bit.__fgpio_shorts.__SHORTL.__shortl
#define FIOSETL_bit       FIOSET_bit.__fgpio_shorts.__SHORTL.__shortl_bit
#define FIOSETU           FIOSET_bit.__fgpio_shorts.__SHORTU.__shortu
#define FIOSETU_bit       FIOSET_bit.__fgpio_shorts.__SHORTU.__shortu_bit

#define FIOCLR_bit         (*((volatile __fgpio_bits *) 0x3FFFC01C))
#define FIOCLR0           FIOCLR_bit.__fgpio_bytes.__BYTE0.__byte0
#define FIOCLR0_bit       FIOCLR_bit.__fgpio_bytes.__BYTE0.__byte0_bit
#define FIOCLR1           FIOCLR_bit.__fgpio_bytes.__BYTE1.__byte1
#define FIOCLR1_bit       FIOCLR_bit.__fgpio_bytes.__BYTE1.__byte1_bit
#define FIOCLR2           FIOCLR_bit.__fgpio_bytes.__BYTE2.__byte2
#define FIOCLR2_bit       FIOCLR_bit.__fgpio_bytes.__BYTE2.__byte2_bit
#define FIOCLR3           FIOCLR_bit.__fgpio_bytes.__BYTE3.__byte3
#define FIOCLR3_bit       FIOCLR_bit.__fgpio_bytes.__BYTE3.__byte3_bit
#define FIOCLRL           FIOCLR_bit.__fgpio_shorts.__SHORTL.__shortl
#define FIOCLRL_bit       FIOCLR_bit.__fgpio_shorts.__SHORTL.__shortl_bit
#define FIOCLRU           FIOCLR_bit.__fgpio_shorts.__SHORTU.__shortu
#define FIOCLRU_bit       FIOCLR_bit.__fgpio_shorts.__SHORTU.__shortu_bit


/* Memory Accelerator Module (MAM) */
#define MAMCR_bit          (*((volatile __mamcr_bits *) 0xE01FC000))
#define MAMTIM_bit         (*((volatile __mamtim_bits *)0xE01FC004))
#define MEMMAP_bit         (*((volatile __memmap_bits *)0xE01FC040))

/* Phase Locked Loop (PLL) */
#define PLLCON_bit         (*((volatile __pllcon_bits *) 0xE01FC080))
#define PLLCFG_bit         (*((volatile __pllcgf_bits *) 0xE01FC084))
#define PLLSTAT_bit        (*((volatile __pllstat_bits *)0xE01FC088))
#define PLLFEED_bit        (*((volatile __pllfeed_bits *)0xE01FC08C))

/* APB Divider */
#define APBDIV_bit         (*((volatile __apbdiv_bits *) 0xE01FC100))

/* Power Control */
#define PCON_bit           (*((volatile __pcon_bits *) 0xE01FC0C0))
#define PCONP_bit          (*((volatile __pconp_bits *) 0xE01FC0C4))


/* External Interrupts */
#define EXTINT_bit         (*((volatile __extint_bits *) 0xE01FC140))
#define EXTWAKE_bit        (*((volatile __extwake_bits *) 0xE01FC144))
#define EXTMODE_bit        (*((volatile __extmode_bits *) 0xE01FC148))
#define EXTPOLAR_bit       (*((volatile __extpol_bits *) 0xE01FC14C))

/* Timer 0 */
#define T0IR_bit           (*((volatile __ir0_bits *) 0xE0004000))
#define T0TCR_bit          (*((volatile __tcr_bits *) 0xE0004004))
#define T0MCR_bit          (*((volatile __mcr_bits *) 0xE0004014))
#define T0CCR_bit          (*((volatile __ccr0_bits *) 0xE0004028))
#define T0EMR_bit          (*((volatile __emr_bits *) 0xE000403C))
#define T0CTCR_bit         (*((volatile __tctcr_bits *) 0xE0004070))
#define T0PWMCON_bit       (*((volatile __tpwrcon_bits *) 0xE0004074))

/* Timer 1 */
#define T1IR_bit           (*((volatile __ir1_bits *) 0xE0008000))
#define T1TCR_bit          (*((volatile __tcr_bits *) 0xE0008004))
#define T1MCR_bit          (*((volatile __mcr_bits *) 0xE0008014))
#define T1CCR_bit          (*((volatile __ccr1_bits *) 0xE0008028))
#define T1EMR_bit          (*((volatile __emr_bits *) 0xE000803C))
#define T1CTCR_bit         (*((volatile __tctcr_bits *) 0xE0008070))
#define T1PWMCON_bit       (*((volatile __tpwrcon_bits *) 0xE0008074))

/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
#define U0IER_bit	   (*((volatile __uartier0_bits *) 0xE000C004))
#define U0FCR_bit      (*((volatile __uartfcriir_bits *) 0xE000C008))
#define U0LCR_bit      (*((volatile __uartlcr_bits *) 0xE000C00C))		
#define U0LSR_bit	   (*((volatile __uartlsr_bits *) 0xE000C014))
#define U0MSR_bit      (*((volatile __uartmsr_bits *) 0xE000C018))
#define U0ACR_bit      (*((volatile __uartacr_bits *) 0xE000C020))
#define U0FDR_bit      (*((volatile __uartfdr_bits *) 0xE000C028))
#define U0TER_bit      (*((volatile __uartter_bits *) 0xE000C030))

/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
#define U1IER_bit      (*((volatile __uartier1_bits *) 0xE0010004))
#define U1FCR_bit      (*((volatile __uartfcriir_bits *) 0xE0010008))
#define U1LCR_bit      (*((volatile __uartlcr_bits *) 0xE001000C))
#define U1MCR_bit      (*((volatile __uartmcr_bits *) 0xE0010010))
#define U1LSR_bit      (*((volatile __uartlsr_bits *) 0xE0010014))
#define U1MSR_bit      (*((volatile __uartmsr_bits *) 0xE0010018))
#define U1ACR_bit      (*((volatile __uartacr_bits *) 0xE0010020))
#define U1FDR_bit      (*((volatile __uartfdr_bits *) 0xE0010028))
#define U1TER_bit      (*((volatile __uartter_bits *) 0xE0010030))

/* Inter-Integrated Circuit interface 0 (I2C0) */
#define I2C0CONSET_bit (*((volatile __i2conset_bits *) 0xE001C000))
#define I2C0STAT_bit   (*((volatile __i2stat_bits *) 0xE001C004))
#define I2C0DAT_bit    (*((volatile __i2dat_bits *) 0xE001C008))
#define I2C0ADR_bit    (*((volatile __i2adr_bits *) 0xE001C00C))
#define I2C0SCLH_bit   (*((volatile __i2scl_bits *) 0xE001C010))
#define I2C0SCLL_bit   (*((volatile __i2scl_bits *) 0xE001C014))
#define I2C0CONCLR_bit (*((volatile __i2conclr_bits *) 0xE001C018))

/* Serial Peripheral Interface 0 (SPI0) */
#define S0SPCR_bit         (*((volatile __spcr_bits *) 0xE0020000))
#define S0SPSR_bit         (*((volatile __spsr_bits *) 0xE0020004))
#define S0SPDR_bit         (*((volatile __spdr_bits *) 0xE0020008))
#define S0SPCCR_bit        (*((volatile __spccr_bits *) 0xE002000C))
#define S0SPINT_bit        (*((volatile __spint_bits *) 0xE002001C))

/* Real Time Clock (RTC) */
#define ILR_bit            (*((volatile __ilr_bits *) 0xE0024000))
#define CTC_bit            (*((volatile __ctc_bits *) 0xE0024004))
#define CCR_bit            (*((volatile __rtcccr_bits *) 0xE0024008))
#define CIIR_bit           (*((volatile __ciir_bits *) 0xE002400C))
#define AMR_bit            (*((volatile __amr_bits *) 0xE0024010))
#define CTIME0_bit         (*((volatile __ctime0_bits *) 0xE0024014))
#define CTIME1_bit         (*((volatile __ctime1_bits *) 0xE0024018))
#define CTIME2_bit         (*((volatile __ctime2_bits *) 0xE002401C))
#define SEC_bit            (*((volatile __sec_bits *) 0xE0024020))
#define MIN_bit            (*((volatile __min_bits *) 0xE0024024))
#define HOUR_bit           (*((volatile __hour_bits *) 0xE0024028))
#define DOM_bit            (*((volatile __dom_bits *) 0xE002402C))
#define DOW_bit            (*((volatile __dow_bits *) 0xE0024030))
#define DOY_bit            (*((volatile __doy_bits *) 0xE0024034))
#define MONTH_bit          (*((volatile __month_bits *) 0xE0024038))
#define YEAR_bit           (*((volatile __year_bits *) 0xE002403C))
#define ALSEC_bit          (*((volatile __sec_bits *) 0xE0024060))
#define ALMIN_bit          (*((volatile __min_bits *) 0xE0024064))
#define ALHOUR_bit         (*((volatile __hour_bits *) 0xE0024068))
#define ALDOM_bit          (*((volatile __dom_bits *) 0xE002406C))
#define ALDOW_bit          (*((volatile __dow_bits *) 0xE0024070))
#define ALDOY_bit          (*((volatile __doy_bits *) 0xE0024074))
#define ALMON_bit          (*((volatile __month_bits *) 0xE0024078))
#define ALYEAR_bit         (*((volatile __year_bits *) 0xE002407C))
#define PREINT_bit         (*((volatile __preint_bits *) 0xE0024080))
#define PREFRAC_bit        (*((volatile __prefrac_bits *) 0xE0024084))

/* Analog/Digital Converter (ADC) */
#define ADCR_bit           (*((volatile __adcr_bits *) 0xE0034000))
#define ADGDR_bit          (*((volatile __adgdr_bits *) 0xE0034004))
#define ADINTEN_bit        (*((volatile __adinten_bits *) 0xE003400C))
#define ADDR0_bit          (*((volatile __addr_bits *) 0xE0034010))
#define ADDR1_bit          (*((volatile __addr_bits *) 0xE0034014))
#define ADDR2_bit          (*((volatile __addr_bits *) 0xE0034018))
#define ADDR3_bit          (*((volatile __addr_bits *) 0xE003401C))
#define ADDR4_bit          (*((volatile __addr_bits *) 0xE0034020))
#define ADDR5_bit          (*((volatile __addr_bits *) 0xE0034024))
#define ADDR6_bit          (*((volatile __addr_bits *) 0xE0034028))
#define ADDR7_bit          (*((volatile __addr_bits *) 0xE003402C))
#define ADSTAT_bit         (*((volatile __adstat_bits *) 0xE0034030))

/* Inter-Integrated Circuit interface 1 (I2C1) */
#define I2C1CONSET_bit     (*((volatile __i2conset_bits *) 0xE005C000))
#define I2C1STAT_bit       (*((volatile __i2stat_bits *) 0xE005C004))
#define I2C1DAT_bit        (*((volatile __i2dat_bits *) 0xE005C008))
#define I2C1ADR_bit        (*((volatile __i2adr_bits *) 0xE005C00C))
#define I2C1SCLH_bit       (*((volatile __i2scl_bits *) 0xE005C010))
#define I2C1SCLL_bit       (*((volatile __i2scl_bits *) 0xE005C014))
#define I2C1CONCLR_bit     (*((volatile __i2conclr_bits *) 0xE005C018))

/* Synchronous Serial Port interface (SSP) */
#define SSPCR0_bit         (*((volatile __sspcr0_bits*) 0xE0068000))
#define SSPCR1_bit         (*((volatile __sspcr1_bits *) 0xE0068004))
#define SSPDR_bit          (*((volatile __sspdr_bits *) 0xE0068008))
#define SSPSR_bit          (*((volatile __sspsr_bits *) 0xE006800C))
#define SSPCPSR_bit        (*((volatile __sspcpsr_bits *) 0xE0068010))
#define SSPIMSC_bit        (*((volatile __sspimsc_bits *) 0xE0068014))
#define SSPRIS_bit         (*((volatile __sspris_bits *) 0xE0068018))
#define SSPMIS_bit         (*((volatile __sspmis_bits *) 0xE006801C))
#define SSPICR_bit         (*((volatile __sspicr_bits *) 0xE0068020))

/* Timer 2 */
#define T2IR_bit           (*((volatile __ir0_bits *) 0xE0070000))
#define T2TCR_bit          (*((volatile __tcr_bits *) 0xE0070004))
#define T2MCR_bit          (*((volatile __mcr_bits *) 0xE0070014))
#define T2CCR_bit          (*((volatile __ccr0_bits *) 0xE0070028))
#define T2EMR_bit          (*((volatile __emr_bits *) 0xE007003C))
#define T2CTCR_bit         (*((volatile __tctcr_bits *) 0xE0070070))
#define T2PWMCON_bit       (*((volatile __tpwrcon_bits *) 0xE0070074))

/* Timer 3 */
#define T3IR_bit           (*((volatile __ir3_bits *) 0xE0074000))
#define T3TCR_bit          (*((volatile __tcr_bits *) 0xE0074004))
#define T3MCR_bit          (*((volatile __mcr_bits *) 0xE0074014))
#define T3EMR_bit          (*((volatile __emr_bits *) 0xE007403C))
#define T3CTCR_bit         (*((volatile __tctcr_bits *) 0xE0074070))
#define T3PWMCON_bit       (*((volatile __tpwrcon_bits *) 0xE0074074))


/* Reset Source Identification */
#define RSIR_bit           (*((volatile __rsir_bits *) 0xE01FC180))

/* Syscon Miscellaneous */
#define SCS_bit            (*((volatile __scs_bits *) 0xE01FC1A0))

/* Watchdog timer */
#define WDMOD_bit          (*((volatile __wdmod_bits *) 0xE0000000))
#define WDFEED_bit         (*((volatile __wdfeed_bits *) 0xE0000008))

/***************************************************************************
 **
 **  Interrupt vector table
 **
 ***************************************************************************/
#define RESETV          0x00  /* Reset                              */
#define UNDEFV          0x04  /* Undefined instruction              */
#define SWIV            0x08  /* Software interrupt                 */
#define PABORTV         0x0c  /* Prefetch abort                     */
#define DABORTV         0x10  /* Data abort                         */
#define IRQV            0x18  /* Normal interrupt                   */
#define FIQV            0x1c  /* Fast interrupt                     */

/***************************************************************************
 **
 **  VIC Interrupt channels
 **
 ***************************************************************************/
#define VIC_WDT          0    /* Watchdog                           */
#define VIC_DEBUGRX      2    /* Embedded ICE, DbgCommRx            */
#define VIC_DEBUGTX      3    /* Embedded ICE, DbgCommTx            */
#define VIC_TIMER0       4    /* Timer 0 (Match 0-2 Capture 0-2)    */
#define VIC_TIMER1       5    /* Timer 1 (Match 0-3 Capture 0-3)    */
#define VIC_UART0        6    /* UART 0  (RLS, THRE, RDA, CTI)      */
#define VIC_UART1        7    /* UART 1  (RLS, THRE, RDA, CTI, MSI) */
#define VIC_I2C0         9    /* I2C     (SI)                       */
#define VIC_SPI         10    /* SPI     (SPIF, MODF)               */
#define VIC_SSP         11    /* SPI1 (SSP)                         */
#define VIC_PLL         12    /* PLL lock (PLOCK)                   */
#define VIC_RTC         13    /* RTC     (RTCCIF, RTCALF)           */
#define VIC_EINT0       14    /* External interrupt 0 (EINT0)       */
#define VIC_EINT1       15    /* External interrupt 1 (EINT1)       */
#define VIC_EINT2       16    /* External interrupt 2 (EINT2)       */
#define VIC_ADC         18    /* A/D Converter 0 end of conversion  */
#define VIC_I2C1        19    /* I2C     (SI)                       */
#define VIC_TIMER2      26    /* Timer 2 (Match 0-2 Capture 0-2)    */
#define VIC_TIMER3      27    /* Timer 3 (Match 0-3)                */

#endif //__IOCONFIG_H
