#ifndef _SYSTEM_H_
#define _SYSTEM_H_

/*
*********************************************************************************************
*									SYSTEM INITIALIZATION 
*
* Example: the target Processor clock Fcclk is 60MHz at crystal frequency Fosc = 12MHz
* M=Fcclk/Fosc=60MHz/12MHz=5; Value written to MSEL bits in PLL0CFG is M-1, i.e. it is 4
* PLL0CFG[4:0]=4. There is a current controlled oscillator (CCO) with Fcco restricted as
* Fcco=P*Fcclk*2, 156MHz<Fcco<320MHz. 
* Now Fcclk=60MHz, thus P=2 by inspection. PSEL=PLL0CFG[6:5]=01	 (refer to manual for this)
* PLL0CFG=0x24
* PCLKDIV defines the peripheral clock divider value in 1,2, or 4
* It finally defines VPB Divider to allow power savings when an application does not require 
* any peripherals to run at the full processor rate.
* PCLKDIV defines value of 	1 for Pclk=Fcclk;  	full speed
*							2 for Pclk=Fcclk/2; half speed
*							4 for Pclk=Fcclk/4.	quarter speed
*********************************************************************************************
*/
#define Fosc		12000000	//define the external crystal frequency
#define M			5			//PLL multiplier for processor clock Fcclk, M from 1 to 32!
#define PSEL_		1			//Value of PSEL bits in 0(P=1),1(P=2),2(P=4),3(P=8); 
								//must satisfy the requirement of Fcco
#define PCLKDIV		4			//Peripheral clock divider value






void sysInit(void);

#endif
